Learning Library · Buses and decoding · 2
I²C and SPI
Unlike UART, both of these buses send a clock alongside the data, so the receiver never has to guess the bit timing. I²C does it with two shared wires and an address in every message. SPI uses separate wires for each direction and a chip-select line per device, and goes much faster.
Traces as a logic analyzer or a scope's digital channels would show them. Coloured boxes are the decoded fields. In I²C, the dots on SCL mark where the receiver samples SDA. In SPI, MISO stays high: the device is replying 0xFF.
I²C: two wires, many devices
I²C uses a clock line (SCL) and a data line (SDA), shared by every device on the bus. Both lines are open-drain: devices only ever pull them low, and pull-up resistors bring them back high. Every transaction follows the same pattern:
- Start: SDA falls while SCL is high. That is the only time SDA may change with the clock high, apart from stop.
- Address: seven bits, most significant first, then one read/write bit.
- ACK: the addressed device pulls SDA low for one clock to say it is there. If nobody answers, SDA stays high: a NACK.
- Data: eight bits per byte, each followed by an ACK from the receiver.
- Stop: SDA rises while SCL is high.
Standard I²C runs at 100 kHz, Fast mode at 400 kHz, and Fast-mode Plus at 1 MHz. The pull-up resistors and the bus capacitance set how quickly the lines rise, which is what limits speed.
SPI: four wires, full speed
SPI uses a clock (SCLK), a data line from controller to device (MOSI), a data line back (MISO), and a chip select (CS) for each device. Pulling CS low selects the device. There is no address and no acknowledgment, so every clock edge carries data, in both directions at once. Push-pull outputs let SPI run at tens of megahertz.
The clock's idle level and which edge samples the data are set by the SPI mode, 0 to 3. This explainer shows mode 0: clock idles low, data is sampled on the rising edge. A decoder set to the wrong mode reads every byte shifted by one bit.
Try this
- Send "Hi" over I²C at 100 kHz. The address byte and three ACKs add 11 clocks to the 16 data bits, and the message takes about 280 µs.
- Switch to SPI at 10 MHz. The same two bytes take 1.6 µs.
- Change the I²C address and watch the first decoded field change while the data stays the same.
To decode either bus on an oscilloscope, connect a channel to each line, set the decoder's thresholds to about half the logic voltage, and trigger on the start condition (I²C) or the falling edge of CS (SPI). Make sure the capture window holds the whole message at a sample rate several times the clock frequency.
Decode the bus on your bench. Mixed-signal oscilloscopes with serial bus decoding.
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